Measured across typical samples, the PUMD20 family supports up to 50 V VCE and 100 mA continuous collector current. Featuring integrated base and base‑emitter resistors (R1 = 2.2 kΩ, R2 = 2.2 kΩ), it significantly simplifies drive circuitry. This reference provides engineers with an implementable guide covering pinout, electrical specs, and design strategies for US-based engineering teams. Overview & Key Specifications Parameter Typical / Max Test Condition / Note Polarity NPN / PNP complementary pair Resistor‑equipped pair VCE Max 50 V Absolute maximum rating IC Max (Continuous) 100 mA Package and SOA limited Built‑in Resistors R1 = 2.2 kΩ, R2 = 2.2 kΩ Base → Internal resistor network VCE(sat) Typical: low hundreds of mV Specified at specific IC Table: Compact PUMD20 summary. Use worst‑case values for thermal and saturation budgeting. Pre-biased Design in Practice "Pre‑biased" means each transistor includes internal resistors that set base bias and ensure a defined "off" state. For a typical 3.3 V MCU pin, the calculation is: IB ≈ (3.3V − 0.7V) / 2.2kΩ ≈ 1.18 mA. Expect 20–30 mA collector drive under conservative hFE assumptions. Pinout & Package Details SOT363 / SC‑88 Configuration The top‑view SOT363 package features two mirrored single‑transistor cells. An orientation marker identifies Pin 1. Pair A: Base, Collector, Emitter Pair B: Base, Collector, Emitter (Mirrored) Footprint Notes Area: 1.6 × 1.6 mm | Pitch: 0.5 mm Recommendation: Use 60–80% solder paste coverage. Ensure 0.25–0.3 mm stencil aperture reduction for outer pads to prevent tombstoning. Electrical Performance Metrics Max Operating Voltage (VCE) 50V Peak Continuous Current (IC) 100mA Maximum Thermal Behavior: Junction temperature rise is significant due to the high θJA of small packages. Formula: Tj = Ta + θJA × Pd. Design & Application Guidelines Low-Side Switching Ideal for MCU drives. With IB ≈ 1.18 mA and min hFE = 20, IC reaches 24 mA. For higher currents, use an external driver or parallel resistors. PCB Layout & EMC Keep base traces short and shielded by ground pours. Place decoupling capacitors near the load supply, not the transistor base. Use RC snubbers for inductive loads. Bench Test Checklist [✓] Verify orientation and solder joint integrity (Pin 1 check). [✓] Measure VCE(sat) at the target collector current. [✓] Perform thermal inspection using IR imaging under peak load. [✓] Validate leakage currents are within datasheet budgets when "off". FAQ — Common Questions What base current can I expect from a 3.3 V MCU pin? + With VGPIO = 3.3 V and VBE ≈ 0.7 V, the internal 2.2 kΩ resistor results in IB ≈ (3.3 − 0.7) / 2.2k ≈ 1.18 mA. Always use a conservative hFE for your final IC calculations. How do I estimate the junction temperature? + Use the formula Tj = Ta + (θJA × Pd). Measure Pd as VCE × IC. Ensure you account for the duty cycle in PWM applications and use the worst-case ambient temperature (Ta). How to search for equivalent pre‑biased parts? + Match the polarity (NPN/PNP), VCE (≥50V), IC (≥100mA), and package (SOT363). Specifically verify resistor values (2.2k/2.2k) and thermal limits, as slight variances in internal R values impact switching thresholds. Conclusion The PUMD20 family is a versatile, space-saving solution for small-signal switching. By integrating biasing resistors, it reduces component count and PCB complexity while maintaining robust 50V/100mA ratings. Compact Specs50V VCE, 100mA IC, R1/R2 = 2.2kΩ. MCU FriendlyDirect logic drive with ~1.18mA base current. ReliabilityHigh θJA requires careful thermal derating.

Point: The PUMD2 family packs pre-biased NPN/PNP transistor pairs with built-in resistors and up to 50 V blocking and ~100 mA switching capability.Evidence: The PUMD2 datasheet lists the device as a dual resistor-equipped transistor (RET) intended for low-power switching.Explanation: This combination reduces external component count and simplifies input interfacing for compact, high-density designs.PUMD2-card" style="animation-delay: 0.2s;"> PUMD2-badge" style="margin-bottom: 20px;">Design Strategy Point: This guide extracts critical parameters and converts them into practical layout, thermal, and testing actions. Evidence: Recommended test conditions and absolute limits are derived directly from standardized datasheet test tables. Explanation: Adhering to these values and derating advice during schematic capture and board bring-up prevents premature field failures. PUMD2-section"> Quick Overview & Common Use Cases What PUMD2 Actually Is Point: The device is a dual transistor with integrated base resistors in a small SMD envelope. Evidence: The datasheet describes two complementary transistor halves with dedicated base resistor networks (R1 and R2). Explanation: One package provides two pre-biased transistor halves for low-current switching and level translation, effectively cutting BOM costs and saving PCB real estate. Typical Applications & Constraints Point: Use the device for low-current loads and signal interfacing; avoid heavy power tasks. Evidence: Rated blocking voltage (50V) and collector current (100mA) position it for LEDs and logic drivers. Explanation: It is ideal for LED indicators, small relay drivers, and signal translators. Avoid high-current switching or high-thermal-margin environments where discrete MOSFETs are more appropriate. PUMD2-section"> Key Electrical Specs & Absolute Maximum Ratings Absolute Maximum Ratings: Safety Boundaries Understand absolute maxima as hard limits, not operating targets. Exceeding these risks avalanche breakdown or thermal runaway. Parameter Typical Limit Units Visual Scale Design Note VCEO (Collector-Emitter Voltage) 50 V Derate for transients and inductive spikes. IC (Collector Current) 100 mA Limit continuous current to a safer fraction ( Pd (Power Dissipation) ~350 mW Highly dependent on PCB copper and Ta. Tj max / Tstg 150 / -55..150 °C Follow junction derating curves strictly. Recommended Operating Conditions Point: Operate inside recommended conditions for long-term reliability. Evidence: Datasheets differentiate absolute max from recommended ranges for Ta and Ic. Explanation: Always specify Ta = 25°C test conditions when verifying. Select continuous collector currents significantly below 100 mA to provide thermal margin for elevated ambient temperatures. PUMD2-section"> Pinout, Package & Footprint Guide Pinout Explanation & Pin Functions Point: Map pin numbers to transistor terminals precisely before layout. Evidence: The datasheet provides a top-view pin numbering scheme with B, C, E, and internal resistor connections for both NPN and PNP halves. Pin 1: Emitter 1 (NPN) Pin 2: Base 1 (NPN) Pin 3: Collector 2 (PNP) Pin 4: Emitter 2 (PNP) Pin 5: Base 2 (PNP) Pin 6: Collector 1 (NPN) Package Variants & Footprint Tips Footprint choices directly affect soldering yield and thermal dissipation. Use a modest solder paste stencil (10–12 mil aperture reduction) and provide thermal copper tied to large pads to improve heat spreading if continuous dissipation is expected. PUMD2-section"> Electrical Characteristics & Thermal Behavior DC & Switching Performance Check gain (hFE), VCE(sat), and input leakage. Reproduce test points in the lab (e.g., Ic = 10–50 mA) to confirm performance. If your switching speed requirements are high, verify VCE(sat) at the expected Ic. Thermal Derating Logic Calculate Pd = VCE × IC. If the Pd limit is ~350 mW, a VCE of 10 V allows only ~35 mA continuous current. Always increase copper area or reduce VCE to ensure the junction stays cool. PUMD2-section"> Typical Circuits & Application Examples PUMD2-card" style="border-left-color: #2ecc71;"> Simple Low-side Switch Implement one transistor half as a low-side switch for LEDs. The internal base resistors provide a defined idle bias. For inductive loads, always include a flyback clamp diode to protect the collector from voltage spikes. PUMD2-card" style="border-left-color: #9b59b6;"> Complementary Dual-driver Uses Use both halves for push-pull configurations or level shifting. Warning: Avoid simultaneous conduction of complementary halves. Manage dead time carefully and include ESD protection if pins interface with external connectors. PUMD2-section"> Testing, Troubleshooting & Design Checklist Lab Procedures: Verify pin mapping via continuity. VCE Limits: Test insulation and breakdown. Thermal Rise: Measure temperature under steady load. Transients: Capture switching spikes with an oscilloscope. PCB Layout: Keep collector/emitter traces short. BOM Check: Verify marking codes and reel orientation. Thermal: Add dedicated copper pours for heat sinking. Sourcing: Confirm package variant (SOT-363 vs others). PUMD2-section" style="background: #2c3e50; color: #fff; padding: 30px; border-radius: 12px;"> Summary Verify absolute maximums (50 V VCEO, 100 mA) and apply conservative margins. Confirm exact pinout: label silkscreen and map B/C/E for each half carefully. Derate power using Pd = VCE × IC and optimize PCB copper for thermal headroom. Utilize the testing checklist during bring-up to catch assembly or footprint errors early. PUMD2-section"> Frequently Asked Questions How do I validate the device pinout on my board? Use continuity and a bench multimeter to map each pin to the schematic symbol. Compare results to the datasheet top-view numbering and confirm silkscreen orientation before placing parts to prevent mirror-image mistakes. What test points should I capture to reproduce datasheet numbers? Capture VCE(sat) at the specified Ic and Ib test points, hFE vs. Ic, steady-state thermal rise at continuous load, and switching transients with a high-bandwidth scope. Use Ta = 25°C as your baseline. How should I choose continuous current limits for reliability? Limit continuous IC to a safe fraction of the absolute max (often d for your expected VCE and design PCB copper to keep junction temperatures well below the 150°C maximum under worst-case ambient conditions.

Datasheet at a glance: key specs & how to read them Headline specs summary Primary ratings to list succinctly are summarized below for engineering scan-ability: Spec Name Symbol Condition Value Collector-Emitter Voltage VCE(max) Absolute Max 50 V Collector Current IC(cont) Continuous 100 mA Junction Temperature Tj,max Operating 150 °C Package Type - SOT-363 UMT-6 Style How to interpret datasheet tables & figures Focus on sections: Absolute Maximum Ratings, Thermal Characteristics (θJA/θJC), DC Electrical Characteristics, Switching Characteristics, and Typical Performance Graphs. Annotate ambiguous conditions such as Ta vs Tj and continuous vs. pulse IC. Flag any missing pulse durations or waveform definitions as a datasheet caveat so readers can request clarifications if needed. Absolute maximum ratings & SOA: 50V and 100mA explained 50V rating: breakdown, voltages, and margin planning An absolute VCE = 50V means the device must not be exposed to higher sustained VCE; avalanche behavior can occur near that edge. Recommended practice is 20–30% derating for continuous operation, so limit operating VCE to ~35–40V in noisy environments and add clamp diodes or RC snubbers to handle inductive transients. Voltage Safety Margin Visualization Absolute Max (50V) Safe Margin (35V) 100mA limit: continuous vs. pulse and peak handling Continuous IC = 100mA sets the steady‑state current ceiling; pulsed capability may be higher but requires explicit pulse width and duty data from the datasheet. For switching bursts, calculate Ipk × VCE pulse dissipation separately and ensure thermal time constants allow transient energy without exceeding Tj,max. Engineering Tip: Use 20–30% current derating in elevated ambient temperatures or crowded PCBs to maintain long-term reliability. Electrical characteristics & dynamic performance DC characteristics: VCE(sat), hFE, leakage currents Typical VCE(sat) at specified IC/IB should be used to compute dissipation: P = VCE(sat) × IC. For example, at 100mA and VCE(sat) = 0.2 V, dissipation is 0.02 W per device—negligible thermally—but worst‑case VCE(sat) may be higher. hFE typically varies strongly with IC; account for low gain at high IC when sizing base resistors. Switching characteristics: rise/fall times, storage time, capacitances Switching times and device charge determine suitability for frequency targets. If tf and tr are tens to hundreds of nanoseconds, the device suits kHz to low MHz signals. Account for input/output capacitances when designing drive circuits, and estimate switching loss from energy per transition using measured or datasheet charge numbers. Application examples & design guidelines Application case study: low-side driver & signal-level translator A typical low‑side driver using the pre‑biased transistor: pick base resistor such that IB ≈ IC/hFE_min; with internal bias resistors, calculate external resistor adjustment to achieve IB for 100mA load. Example: if hFE_min = 50, IB ≈ 2 mA for IC = 100 mA; verify VCE(sat) and compute P = VCE × IC under worst‑case VCE(sat) for thermal margin before layout. PCB layout, thermal management & package considerations Thermal path in small packages relies on PCB copper. Use maximum allowable power and θJA to estimate ΔTj = Pd × θJA. If Pd = 0.5 W with θJA = 300 °C/W, it yields a 150 °C rise (unacceptable). Spread copper, add vias to inner planes, and derate operating power accordingly. Validation, testing & troubleshooting checklist Recommended tests & measurement procedures Perform incremental VCE breakdown sweep with current limit to observe avalanche knee. Measure VCE(sat) at target IC and IB. Execute pulse testing at representative pulse widths to validate transient current capability. Use current limiting supplies and scope with adequate bandwidth. Common failure modes, signatures & mitigations Typical failures include over‑voltage breakdown, thermal runaway, and overstress. Symptom triage: rising VCE(sat) suggests base drive or junction damage; increased leakage with temperature indicates junction stress. Mitigations include increasing margins, adding clamps, and improving PCB thermal relief. Summary The PUMD2’s 50V and 100mA limits imply clear operating envelopes: derate from absolute maxima, validate thermal path, and verify switching losses under real waveforms. 1. DeratingUse 20–30% voltage/current derating for reliable margins. 2. ThermalCompute junction temperature from Pd and θJA. 3. ValidationValidate via incremental breakdown and saturation tests. Key summary points Derate the 50V absolute rating by 20–30% in practice to protect against transients and ensure a robust safe operating area for the PUMD2. Respect the 100mA continuous IC limit; size base drive using hFE_min and validate pulse handling with measured current and duty cycle. Thermal design is decisive: calculate ΔTj = Pd × θJA, spread PCB copper and add vias to keep junction temperature below limits. FAQ How should engineers validate PUMD2 VCE breakdown safely? Validate breakdown using an incremental voltage sweep with a current‑limited source, monitor current and temperature, and stop at the datasheet absolute limit. Use clamps for inductive environments and interpret the breakdown knee conservatively, applying derating and retesting under elevated ambient to confirm margin. What is the recommended approach to ensure PUMD2 meets the 100mA continuous spec? Design for IC ≤ 100mA steady‑state, calculate base resistor using worst‑case hFE_min, and run thermal tests: measure VCE(sat) at operating IC and compute Pd. Include a 20–30% current margin in high ambient or dense PCB layouts. Which quick lab checks should be run before production when using PUMD2? Run three checks: VCE breakdown sweep with current limit, VCE(sat) measurement at target IC/IB, and pulse stress test for transient current behavior. Verify junction temperature with planned Pd and θJA.

Device family & role in designs Point: The PUMD20 is a resistor-equipped, low-current transistor intended as a compact peripheral driver. Evidence: Datasheet descriptions emphasize pre-biased NPN/PNP halves for direct IC input interfacing and small-signal switching. Explanation: That pre-bias simplifies base drive for microcontroller GPIO, replacing discrete transistor-plus-resistor assemblies and saving BOM and board space; the small SMD package makes it well suited for LED indicators, level-shift gates, and IC input pulls in dense layouts. Key datasheet sections to check first Point: Rapid assessment starts with a short list of tables and graphs. Evidence: Engineers should scan the quick-reference table, absolute maximum ratings, DC characteristics, switching characteristics, thermal data, and packaging information. Explanation: When time is limited, inspect the quick-ref → absolute max → DC characteristics → switching sequence to confirm that VCEO, continuous IC, Pd, and rise/fall times meet system requirements before deeper validation. Absolute maximum ratings & thermal limits (data analysis) Absolute maximums to never exceed Point: Absolute maximums define non-recoverable limits and must not be treated as operating targets. Evidence: Datasheet absolute entries include VCEO (50 V), VCBO, IE/IC peak and continuous figures, junction and storage temperatures. Explanation: Treat recommended operating conditions as the design target and reserve a safety margin (for example, ensure VCEO − expected operating voltage ≥ design margin) to account for spikes, tolerance stacks, and aging when selecting the transistor for mixed-voltage logic domains. Thermal resistance and power dissipation Point: Thermal limits set the real usable power budget for the package and determine Pd derating by ambient. Evidence: Datasheet thermal resistance RθJA (package dependent) and maximum junction temperature (typically 150°C) let you convert power into temperature rise; these are the electrical specs that govern continuous dissipation. Explanation: For example, switching a 100 mA load at 50 V (worst-case) would dissipate 5 W if purely resistive—well beyond a small SMD transistor—so designers must compute actual VCE under load and duty cycle and ensure junction temperature stays below limit using RθJA-based calculations and PCB thermal pads. Parameter Typical Value / Note Visual Range VCEO 50 V IC (continuous) up to 100 mA Pd ~ few hundred mW (Ta=25°C) Tj (max) ~150°C Max operating limit Package small SMD SOT-363 or equivalent DC electrical characteristics: currents, voltages, gains (data analysis) Collector/emitter currents & saturation Point: VCE(sat) and continuous IC determine switching headroom and losses for low-side or high-side transistor use. Evidence: The datasheet specifies VCE(sat) at defined IC/IB ratios and provides typical vs guaranteed figures at specified conditions. Explanation: When using the device as a switch, reserve margin by designing with lower-than-max collector current or higher base drive so that VCE(sat) stays low; for a 100 mA load, ensure the chosen IB ratio keeps VCE(sat) within the acceptable voltage drop budget for the driven load. Current gain (hFE) & pre-bias resistors Point: hFE variation across IC and VCE affects required base drive; pre-bias resistors change IB calculation. Evidence: Datasheet tables list hFE ranges at multiple IC points and indicate the device’s built-in resistor network for base bias. Explanation: Use a worked check: pick IC=50 mA and read hFE_min for that current; compute IB_required = IC / hFE_min, then compare to the internal base resistor’s delivered base current at your drive voltage. If internal bias is insufficient, add an external base resistor or driver stage to guarantee saturation under worst-case hFE. Switching characteristics & dynamic behavior (method guide) Turn-on/turn-off times & storage delay Point: Switching parameters quantify dynamic performance and are specified with test conditions. Evidence: Datasheet entries include ton, toff, tr, tf and typically list the RL and VCC used during measurement. Explanation: Read the test conditions carefully—different RL or VCC change measured times. Perform bench verification with the same load conditions and scope timing to validate real-world behavior; prioritize measuring storage delay and toff for fast, repetitive switching to ensure no unexpectedly slow turn-off under pre-bias conditions. How switching affects power & EMI Point: Switching losses and EMI scale with transition energy and frequency. Evidence: Per-event switching loss is roughly 0.5·C·V² or VCE·IC·(transition_time), and average loss multiplies by frequency; datasheet switching times let you estimate these values. Explanation: Minimize EMI and switching losses by controlling dV/dt or dI/dt (snubbers, RC damping), using layout separation for sensitive traces, and considering slower edge rates if thermal margin is tight—these measures preserve device reliability and system compliance. Typical application examples & circuit-level guidance (case study) Common Circuits Used as a low-side switch, input driver, or level-shift element. Example: To drive a 10 mA LED, choose series resistor R = (VCC − Vf − VCE(sat)) / 10 mA. Include VCE(sat) from datasheet in the numerator to keep transistor dissipation within package limits. Failure Modes Failures often trace to thermal stress or inductive spikes. Checklist: Measure VCE under load, confirm package temperature, and verify base bias. Functional tests and IC/IB sweeps are critical for robustness. Design & implementation checklist for engineers (action recommendations) Pre-layout checklist Confirm absolute max margins (VCEO). Compute Pd for expected duty cycles. Select footprint with thermal pads. Add surge/inductive protection (TVS/Snubber). Validation & Production Functional IC/IB sweeps. Thermal profiling at max ambient. Humidity/temp stress testing. Sampling VCE(sat) per lot. Summary Concise recap: Extracting the PUMD20 datasheet’s electrical specs means prioritizing absolute maximums, thermal limits, DC characteristics (IC, VCE(sat), hFE), and switching data to shape layout and drive choices. Actionable next step: run the example IB calculation from H3.2 with your target voltages and load to confirm base drive and VCE(sat) budget. Address thermal margins early, verify switching loss vs. duty cycle, and validate on the bench under worst-case conditions. Key takeaways Prioritize absolute max and design margins for VCEO. Compute thermal dissipation using RθJA. Verify hFE at expected IC for base drive sizing. Estimate switching loss to mitigate EMI issues. FAQ What key numbers should I check first in a PUMD20 datasheet? Start with VCEO (50 V class), continuous IC (up to 100 mA), Pd guidelines and RθJA, and maximum junction temperature. These values quickly tell you whether the transistor family fits your voltage domain, current draw, and thermal envelope before deeper validation. How do I size base drive for the PUMD20 to guarantee saturation? Pick your required IC, read the minimum hFE at that current from the datasheet, compute IB_required = IC / hFE_min, and then compare to the internal/external resistor network. If internal pre-bias cannot supply IB_required under worst-case hFE, add an external base resistor or driver to ensure VCE(sat) remains within your margin. How should I verify thermal dissipation for a given switching frequency? Calculate per-event switching energy using VCE·IC·transition_time (or use device capacitance-based estimates), multiply by frequency for average switching loss, add conduction loss (VCE(sat)·IC·duty), then convert to junction rise with RθJA. Validate with thermal profiling on a populated board under worst-case ambient and duty cycle.